Side-Channel Attack
Recovering secrets from physical leakage, power, timing, EM, or induced faults, rather than by breaking the algorithm. The reason a mathematically sound cipher can still surrender its key.
A side-channel attack recovers a secret by measuring the physical effects of a computation, its power draw, timing, or electromagnetic emission, or by physically disturbing the device, rather than by breaking the cryptographic algorithm on paper. The maths can be flawless and the key still leaks through the silicon that runs it.
What it is
Every real computation has physical cost. Flipping a bit in a register draws current; a table lookup takes time; a multiply radiates a field. When any of those costs depends on a secret value, the secret leaks into a side channel, a signal the designer never intended to expose. Side-channel attacks split into two families: passive analysis, where you observe leakage and correlate it with guesses about the key, and active fault injection, where you push the chip outside its safe operating envelope to make it misbehave in a useful way.
Why it matters
A cipher can be mathematically unbreakable yet hand over its key through the hardware running it. Side channels routinely defeat smartcards, secure elements, TPMs, and embedded crypto that looks unassailable, and on IoT silicon they are the standard fallback once the offline paths are shut: when Secure Boot and Flash Encryption keys are locked in eFuse, you cannot read them, but a power-analysis rig or a well-timed glitch can often recover them or skip the check that enforces them entirely.
How it works
When a chip processes a secret, its instantaneous power draw and EM field correlate with the data and the operations. Collect many traces of the same operation, then apply statistics:
- DPA / CPA (Differential / Correlation Power Analysis) model the power a chip should draw for each key guess, correlate that model against thousands of real traces, and the correct guess produces the sharpest correlation peak, one key byte at a time.
- Timing attacks exploit data-dependent execution time, an early-exit memcmp on a password, or a non-constant-time modular exponentiation, leaking bits through how long the operation runs.
- Fault injection (glitching) briefly drops the supply voltage, injects an extra clock edge, or fires an EM/laser pulse at a precise moment to corrupt one instruction, turning a if (sig_ok) branch into an unconditional pass.
From an attacker's view
A capture rig such as a ChipWhisperer synchronizes to the target, triggers on the operation of interest, and records a power trace over a shunt resistor or an EM probe.
target ── shunt/EM probe ── ChipWhisperer ── PC (attack)
└── trigger (GPIO / I/O event) ─────────┘
For power analysis you average and align traces, then run CPA against a leakage model of the S-box output. For glitching you sweep the glitch offset and width until a boot that should fail instead drops you into a debug shell or an un-authenticated firmware. The same JTAG/SWD pads you would use to debug are often how you halt the core, set the trigger, and confirm the fault landed.
Pitfalls
- Alignment and noise dominate real captures; a misaligned or under-averaged trace set hides a key that a clean one reveals in minutes.
- Fault injection is destructive-adjacent: over-glitching can brick the part, and results are probabilistic, you tune parameters and retry, you do not get a clean one-shot.
- Constant-time code, masking, hiding (jitter, dummy operations), and glitch detectors all raise the bar, so a negative result means "not with this rig and effort", not "immune".